EK-K7-KC705-CES-G-J【PDF 57/62 页】KINTEX-7 FPGA KC705 EVAL KIT

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

XADC Specifications

Table 68: XADC Specifications

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

V CCADC = 1.8V ± 5%, V REFP = 1.25V, V REFN = 0V, ADCCLK = 26 MHz, T j = –40°C to 100°C, Typical values at T j =+40°C

ADC Accuracy (1)

Resolution

12

–

–

Bits

Integral

Nonlinearity (2)

INL

–

–

±3

LSBs

Differential Nonlinearity

Offset Error

Gain Error

Offset Matching

Gain Matching

Sample Rate

DNL

No missing codes, guaranteed monotonic

Offset calibration enabled

Gain calibration disabled

Offset calibration enabled

Gain calibration disabled

–

–

–

–

–

0.1

–

–

–

–

–

–

±1

±6

±0.5

4

0.3

1

LSBs

LSBs

%

LSBs

%

MS/s

Signal to Noise

Ratio (2)

SNR

F SAMPLE = 500KS/s, F IN = 20KHz

60

–

–

dB

RMS Code Noise

External 1.25V reference

On-chip reference

–

–

–

3

2

–

LSBs

LSBs

Total Harmonic

Distortion (2)

THD

F SAMPLE = 500KS/s, F IN = 20KHz

–

70

–

dB

ADC Accuracy at Extended Temperatures

Resolution

T j = –55°C to 125°C

10

–

–

Bits

Integral Nonlinearity (2)

Differential Nonlinearity

INL

DNL

T j = –55°C to 125°C

No missing codes, guaranteed monotonic,

–

–

–

–

±1

±1

LSB

(at 10 bits)

T j = –55°C to 125°C

Analog Inputs (3)

ADC Input Ranges

Maximum External Channel Input Ranges

Unipolar operation

Bipolar operation

Unipolar common mode range (FS input)

Bipolar common mode range (FS input)

Adjacent channels set within these ranges

should not corrupt measurements on adjacent

0

–0.5

0

+0.5

–0.1

–

–

–

–

–

1

+0.5

+0.5

+0.6

V CCADC

V

V

V

V

V

channels

Auxiliary Channel Full

FRBW

250

–

–

KHz

Resolution Bandwidth

On-Chip Sensors

Temperature Sensor Error

Supply Sensor Error

T j = –40°C to 100°C.

T j = –55°C to +125°C

Measurement range of V CCAUX 1.8V ±5%

T j = –40°C to +100°C

Measurement range of V CCAUX 1.8V ±5%

–

–

–

–

–

–

–

–

±4

±6

±1

±2

°C

°C

%

%

T j = –55°C to +125°C

Conversion Rate (4)

Conversion Time - Continuous

Conversion Time - Event

DRP Clock Frequency

ADC Clock Frequency

t CONV

t CONV

DCLK

ADCCLK

Number of ADCCLK cycles

Number of CLK cycles

DRP clock frequency

Derived from DCLK

26

–

8

1

–

–

–

–

32

21

250

26

Cycles

Cycles

MHz

MHz

DS182 (v2.8) March 4, 2014

Product Specification

57

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